from ACgenerator import ACautomaton

if __name__ == '__main__':
    a = ACautomaton()
    words = "he she his hers abandon banana asshole hold".split(' ')
    for word in words:
        a.addWord(word)
    #after add all words, build the relation for all states
    a.make()
    #generate verilog design file & testbench file in 'verilog_output/' directory
    a.genVerilog()

    a.typeTire()
    a.typeTable()
    print("ok")